I don't see anything x86 specific on the article. It focuses on cache coherency, which is applicable to ARM and POWER, and there isn't much about memory model.
Even the description of MOESI is just an introduction and, as the article mentions, actual systems use more complicated protocols.
Edit: if anything, the misconception is that memory barriers have anything to do with cache coherency.
Even the description of MOESI is just an introduction and, as the article mentions, actual systems use more complicated protocols.
Edit: if anything, the misconception is that memory barriers have anything to do with cache coherency.