They claim that the chip has an "MMU". But unfortunately this doesn't seem to be a true RISC-V MMU (according to the Sv32 specification) integrated into the CPU core itself, but just a peripheral designed for memory mapped SPI flash and PSRAM. So as far as I understand there is no true process isolation with page faults and dynamic paging.
Maybe Espressif will notice that there are no RV32 chips with MMU so far (at least to my knowledge); we only have 32 bit MCUs or then only 64 bits for the CPUs. Something like Cortex-A7 is missing.
Baochip looks very interesting, and I highly respect bunnie's work, but I can't realistically say Baochip is a viable option for me, an unprofessional tinkerer.
I'm not sure why you are not sure - S3 was using Cadence's Xtensa 32-bit LX7 dual-core microprocessor, but the article on S31 only mentions "dual core" without too much detail.
That's the SoC. The CPU is a small part of it. For example they could be using an open source design like the CVA6, or a commercial design from someone like Andes.
