x86 is a funny example because it supported unaligned access more than many designs. But ignoring that...
Many CPUs, not just x86, have a "physical bits" length that is less than the address size in the ISA. This saves transistor and power budget, since address buses can be smaller. Of course, it means there is a lower maximum RAM config for that design.
The software would still shuffle around the full ISA word/double word/quad word or whatever. In a typical OS, the MMU and page mapping logic would potentially interpret all the bits to map to the more limited physical address range. It didn't mean storing smaller pointers in your software data structures etc.
I'm not an expert, but I think it varies by ISA whether it is defined how the higher address order bits, above the physical range, are handled. Some may allow applications to set them for address tagging, while the CPU ignores those bits. But, others may require them to all be zeroed to get predictable behavior.
