We're also hitting the limit of DDR5 here (before moving to multiplexed)
I would guess if you had LPCAMM2 located physically around the CPU (one or two on each of the 4 CPU edges) you could also reduce that latency.
We're also hitting the limit of DDR5 here (before moving to multiplexed)
I would guess if you had LPCAMM2 located physically around the CPU (one or two on each of the 4 CPU edges) you could also reduce that latency.