Thanks for the links. This doesn't seem to be a true RISC-V MMU (according to the Sv32 specification) integrated into the CPU core itself, but just a peripheral designed for memory mapped SPI flash and PSRAM. So as far as I understand there is no true process isolation with page faults and dynamic paging.

Sv32 is what every 32-bit RISC-V CPU with an MMU uses. It is a full MMU. You can run Linux on it.

Sure, but what the S31 calls "MMU" is not an Sv32 MMU; therefore my comment.

The documentation states:

> Compliant with RISC-V Sv32 virtual memory scheme

https://documentation.espressif.com/esp32-s31_datasheet_en.p...

Ok, I see. The S3’s "MMU" is just an external-memory mapper, not a virtual-memory MMU. The S31 apparently has both, that mapper plus an architectural CPU-side Sv32 MMU; that offers indeed a lot of interesting possibilities. Even sel4 would run on this machine as it seems. The ARM world has no microcontroller with a true MMU as far as I know. Risc-V now has at least two (here is the other one: https://www.bunniestudios.com/blog/2026/baochip-1x-a-mostly-...).

Cortex-R82 may be the only microcontroller-class ARM core with MMU, but there are few chance for a random dev to develop on them.

The Microchip PIC32MZ MCU has an MMU as well. But not with wireless options in a 8x8 QFN80 package like this ESP32-S31. That's pretty small. No flash though.