I worked on the first PA-RISC workstations (“snakes”, 1989-1991). PA-RISC started as a fairly pure RISC design and was consequently very simple and predictable (short pipeline, 1 delay slot, no complex instructions). The philosophy of the design team was to make the system fast with high clock speeds, short pipelines, and big caches, all big fundamental variables in the performance equation.
Alpha was much more sophisticated but also a lot more complex. The Alpha memory model, in particular, was quite complex with lots of cache control and barrier primitives, IIRC. But it could fly when you got the stars to align.
Edit: Alpha also came out later and PA-RISC also got more complex in later generations.
I feel like PA-RISC actually landed with a handful of useful somewhat-complex instructions. It always struck me as the best architecture from that era, making the correct trade-off of avoided microcode but adopted stuff like completers and shift-and-add operations to minimize instruction count and maximize work done per pipeline.
Yea, there were things like shift and add to do multiplication more efficiently, but they were all one-cycle instructions. It was very regular that way, all designed around a clean pipeline without a stalls or bypassing. But, consequently, it originally didn’t even have integer multiplication or division, just shift and add and a “divide step” that you could repeat/loop. Looking at the instruction set just now, I chuckled at how simple it was. It makes RISC-V look complex.
See: ftp.parisc-linux.org/docs/arch/pa11_acd.pdf
Edit: actually, it did have fixed point multiply via the floating point unit (opcode XMPYU). No fixed point divide, though.
Alpha was much more sophisticated but also a lot more complex. The Alpha memory model, in particular, was quite complex with lots of cache control and barrier primitives, IIRC. But it could fly when you got the stars to align.
Edit: Alpha also came out later and PA-RISC also got more complex in later generations.