Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.
FPGAs were never that maker friendly, due to the whole ecosystem.
Well, the MiSTer project was yet 4 years from being launched back in 2013 when the RISC-5 was implemented in FPGA, so I hope you'd excuse Wirth from not choosing it.