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Which still leaves the question of the cost of the instruction decoder.


It's a balancing act.

Power consumption by the instruction decoder vs the power consumption of additional cache&memory bandwidth.

It's amusing that despite the complaints towards X86 in the 90's nowadays it's actually a really good instruction packing format (though it became really sensible only after AMD64).


The article explicitly addresses that the claim is that it matters for tiny processoors of 1-2 mm2 die size, but for the processor power commonly used in phones or such, that particular cost is insignificant.




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